(1) Field of the Invention
The present invention relates in general to methods for the formation of a device separation film among manufacturing processes for a semiconductor device and more particularly to methods for forming a field oxide film in the semiconductor device.
(2) Description of the Prior Art
The fabrication of an integrated circuit normally begins by processing the semiconductor substrate or wafer to divide the surface area into regions where active devices and substrate embedded interconnects are to be formed, and other regions of dielectric which electrically separate the active device regions. The field oxide dielectric material is routinely silicon dioxide. Though various field oxide formation techniques have been developed and described, the technique commonly known as the localized oxidation of silicon (LOCOS) remains common in the semiconductor industry. In the practice of LOCOS, the active regions of the silicon substrate are masked by a silicon nitride layer, while the field oxide regions are thermally oxidized to form a field dielectric region. Though fundamentally simple and efficient, the LOCOS process and its progeny, such as the FUROX and SWAMI techniques, exhibit deficiencies which reduce yield or performance in the final semiconductor chip product.
The most frequently encountered deficiency in the prior art techniques is commonly known as the bird's beak problem, wherein the field oxide extends under the masking nitride layer to consume some of the usable active area. Additional problems routinely encountered with known field oxide formation processes include stress induced dislocations at the edges of the active regions, and the presence of a relatively non-planar surface in or adjacent the fully formed field oxide. The non-planar recesses or notches at the edges of the active regions often degrade subsequently formed gate oxide. These recesses can trap conductive layer residuals creating short circuit paths. Solutions to theses problems have been proposed, but routinely involve relatively complex or dimensionally critical fabrication sequences which are costly to produce or degrade the semiconductor chip yield.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,472,906 (Shimizu et al.), U.S. Pat No. 5,399,520 (Jang), U.S. Pat. No. 4,986,879 (Lee) and U.S. Pat. No. 5,248,350 (Lee).
Though a number to the techniques successfully attack and solve the bird's beak problem and usually provide relatively planar final concluding surfaces, the approaches routinely create stress induced dislocations at the edges of the active regions and form topologies which include notches or grooves of sufficient dimension to cause the degradation of subsequently formed gate oxide. The stress induced dislocations are often not even recognized, while the notches or grooves are most often visible in the SEM cross-sections of the final structures.